The present invention relates to color linear image sensors, and more particularly, to a active pixel color linear sensors with multi-resolution imaging capabilities.
Commonly-owned co-pending application Ser. No. 09/252,428 titled xe2x80x9cActive Pixel Color Linear Sensor with Line-Packed Pixel Readoutxe2x80x9d, filed even date herewith, and authored by one of the inventors in the instant case describes in detail the operation of an active pixel color linear image sensor operable in one or more desirable pixel readout modes. In particular, the parallel-packed, pixel-packed, and line-packed modes are described, the description of which is incorporated herein by reference together with the accompanying description of the timing and control logic, as well as the active pixel circuit architecture for constructing an active pixel linear sensor employing multi-readout mode functionality.
To summarize herein, parallel-packed readout involves the process whereby during color imaging the values of a set of same-color filtered pixels are sampled and then stored in a linear readout register array and then from there are output one at as time from each linear array. A typical color linear sensor may have three linear arrays (e.g., each storing filtered pixel values for each of the primary colors). In a three register array configuration operating in parallel-packed readout mode, red pixel R1, green pixel G1, and blue pixel B1 are output simultaneously by reading their values from the first column position in each array where they might be stored. In the same fashion, pixels R2, G2 and B2 are next output in parallel from column 2 of the parallel arrays. Thus, parallel readout is achieved by rippling through the arrays on a column-by-column basis. Conventional column decoding schemes are known in the art for enabling each column at the appropriate time during readout.
In pixel-packed mode, the second mode of operation discussed in the co-pending application, a multiplexer or the like is used to multiplex the parallel-stored signals so they are made available (read out) as a single analog data stream. For example, Rl is readout followed by G1 and then B1, all from column 1. Then the next column pixel values from each linear array register is read out in multiplexed fashion, i.e., R2, followed by G2, followed by B2, until all the color pixel values are read out from all the columns.
A third useful read out mode described with particularity in the co-pending application is that of line-packed pixel readout mode. In this mode, all same color pixel values are made available off-chip in serial stream fashion. For example, R1 is read out first followed by R2 then by R3, and so on until all red pixels are read out. This readout method continues until all the green pixels, followed by all the blue pixels, are read out in similar fashion. High speed read out is possible in the line-packed operational mode by storing each subsequent same color pixel value not only on a different column, but also in a different one of the three readout register arrays. In this manner, when shifting through the three register arrays, on a column by column basis, because a subsequent same color pixel value is stored on a different addressable array than the currently read out pixel, the reading out of the subsequent pixel may be initiated even before the current pixel is completely read out, thus resulting in high speed read out.
At the present, there is no single chip solution that provides off-chip serial stream of pixel data in line-packed form, but as has been explained in the co-pending application, such an operational mode is desirable. The most direct (but undesirable) approach to reading out the signals in the line-packed mode is to have the decoding of the readout registers be such that all the R signals are selected sequentially first from a first register array where they might be stored, followed by all the G pixels from a second register array, and finally by all the B pixels from a third register. For purposes explained in the co-pending application, storing consecutively read same-color pixel values in the same register array results in very poor throughput and in the case of a charge coupled device (CCD) color linear sensor, may also require an inordinate amount of extra xe2x80x98on-chipxe2x80x99 and xe2x80x98off-chipxe2x80x99 control. Accordingly, when line-packed readout is desired, sampling and storing consecutive same-color pixels in different register arrays is preferable.
In addition to selecting an appropriate readout mode, it is also desirable to be able to change the resolution setting of the linear sensor since certain applications need not require the full resolution. Often times, half or quarter image resolution is adequate. Regardless of the resolution selected, image sensors still sample and store the contents of every available pixel element in a corresponding storage element. Thus, while in theory reducing resolution should result in faster imaging, this is not the case with, for example, CCD type sensors which require that the entire contents of the linear imaging array be laterally shifted out. To provide lower resolution in such instance, appropriate off-chip AND/NOR decoding may be employed to select a sub-portion of the read out R, G, B pixel element values.
In the case of active pixel sensors, adding on-chip decoding functionality is possible to allow for selectively reading out, for example, every other pixel element (half-resolution: 300 dpi), or every fourth pixel (quarter resolution: 150 dpi), in a 600 dpi full resolution capable image sensor. This might be accomplished using appropriate AND/NOR decoding to selectively enable readout of certain columns in each register array but not others.
A problem with adding such decoding functionality is that in very large length linear array architectures (e.g., 5100 or more columns per row of pixel elements) sufficiently large decoding modules are required, thus impacting the vertical height properties of a single-chip solution, or in the case of an off-chip solution, sufficient real estate is taken up. Large vertical lengths are undesirable from a packaging standpoint.
While the above system level approach does offer the user ways of selecting the desired pixels at the right time, the time it takes for the user to get the all the pixel signals is still the same as that of full resolution even though less resolution is required.
Very large active pixel array sensors employ D flip flop shift registers to effectuate column addressing, instead of AND/NOR type decoders. Shift registers take up less space than say 10-bit column address decoders, and significantly less space than 14-bit decoders as may be employed in very high-resolution linear sensors. While the savings in vertical area could be substantial, shift registers obviously do not offer the flexibility of skipping columns to support variable resolution modes.
It would be desirable to be able to provide active pixel sensors with variable resolution control for faster imaging applications, without significantly impacting chip size.
It would further be desirable to be able to provide color active pixel linear sensors, operable in line packed mode, with variable resolution control for faster imaging applications.
In consideration of the foregoing, one aspect of the invention is to provide active pixel sensors with variable resolution control for faster imaging applications, without significantly impacting chip size.
Another aspect of the invention is to provide color active pixel linear sensors, operable in line packed mode, with variable resolution control for faster imaging applications.
These and other aspects of the invention are achieved by employing shift register logic in combination with decoding logic to provide on-chip column addressing.
The foregoing and still other aspects of the invention, and the advantages thereof, will become fully apparent from the following description.